This invention relates to contact structures to establish electrical contact with contact targets such as contact pads or leads of electronic circuits or devices, and more particularly, to contact structures to be used in a probe card to test semiconductor wafers, semiconductor chips, packaged semiconductor devices or printed circuit boards and the like with an improved frequency bandwidth, pin pitch and contact performance and reliability.
In testing high density and high speed electrical devices such as LSI and VLSI circuits, high performance contact structures, such as probe contactors or test contactors, must be used. The contact structure of the present invention is not limited to the application of testing and burn-in of semiconductor wafers and die, but is inclusive of testing and burn-in of packaged semiconductor devices, printed circuit boards and the like. The contact structure of the present invention can also be used in more general applications including an IC lead, IC packaging, and other electrical connections. However, for the convenience of explanation, the present invention is described mainly with reference to the semiconductor wafer testing.
In the case where semiconductor devices to be tested are in the form of a semiconductor wafer, a semiconductor test system such as an IC tester is usually connected to a substrate handler, such as an automatic wafer prober, to automatically test the semiconductor wafer. Such an example is shown in FIG. 1 in which a semiconductor test system has a test head 100 which is ordinarily in a separate housing and electrically connected to the test system with a bundle of cables. The test head and the substrate handler 400 are mechanically as well as electrically connected with one another by means of a manipulator 500 and a drive motor 510. The semiconductor wafers to be tested are automatically provided to a test position of the test head by the substrate handler.
On the test head 100, the semiconductor wafer to be tested is provided with test signals generated by the semiconductor test system. The resultant output signals from the semiconductor wafer under test (IC circuits formed on the semiconductor wafer) are transmitted to the semiconductor test system. In the semiconductor test system, the output signals are compared with expected data to determine whether the IC circuits on the semiconductor wafer function correctly.
In FIG. 1, the test head 100 and the substrate handler 400 are connected through an interface component 140 consisting of a performance board 120 which is a printed circuit board having electric circuit connections unique to a test head""s electrical footprint, coaxial cables, pogo-pins and connectors. In FIG. 2, the test head 100 includes a large number of printed circuit boards 150 which correspond to the number of test channels (pins) of the semiconductor test system. Each of the printed circuit boards 150 has a connector 160 to receive a corresponding contact terminal 121 of the performance board 120. A xe2x80x9cfrogxe2x80x9d ring 130 is mounted on the performance board 120 to accurately determine the contact position relative to the substrate handler 400. The frog ring 130 has a large number of contact pins 141, such as ZIF connectors or pogo-pins, connected to contact terminals 121, through coaxial cables 124.
As shown in FIG. 2, the test head 100 is placed over the substrate handler 400 and mechanically and electrically connected to the substrate handler through the interface component 140. In the substrate handler 400, a semiconductor wafer 300 to be tested is mounted on a chuck 180. In this example, a probe card 170 is provided above the semiconductor wafer 300 to be tested. The probe card 170 has a large number of probe contactors (such as cantilevers or needles) 190 to contact with contact targets such as circuit terminals or contact pads in the IC circuit on the semiconductor wafer 300 under test.
Electrical terminals or contact receptacles of the probe card 170 are electrically connected to the contact pins 141 provided on the frog ring 130. The contact pins 141 are also connected to the contact terminals 121 of the performance board 120 with coaxial cables 124 where each contact terminal 121 is connected to the printed circuit board 150 of the test head 100. Further, the printed circuit boards 150 are connected to the semiconductor test system through the cable 110 having several hundreds of inner cables.
Under this arrangement, the probe contactors 190 contact the surface (contact targets) of the semiconductor wafer 300 on the chuck 180 to apply test signals to the semiconductor wafer 300 and receive the resultant output signals from the wafer 300. The resultant output signals from the semiconductor wafer 300 under test are compared with the expected data generated by the semiconductor test system to determine whether the IC circuits on the semiconductor wafer 300 performs properly.
FIG. 3 is a bottom view of the probe card 170 of FIG. 2. In this example, the probe card 170 has an epoxy ring on which a plurality of probe contactors 190 called needles or cantilevers are mounted. When the chuck 180 mounting the semiconductor wafer 300 moves upward in FIG. 2, the tips of the cantilevers 190 contact the pads or bumps (contact targets) on the wafer 300. The ends of the cantilevers 190 are connected to wires 194 which are further connected to transmission lines (not shown) formed in the probe card 170. The transmission lines are connected to a plurality of electrodes 197 which further contact the pogo pins 141 of FIG. 2.
Typically, the probe card 170 is structured by a multi-layer of polyimide substrates having ground planes, power planes, signal transmission lines on many layers. As is well known in the art, each of the signal transmission lines is designed to have a characteristic impedance such as 50 ohms by balancing the distributed parameters, i.e., dielectric constant and magnetic permeability of the polyimide, inductances and capacitances of the signal paths within the probe card 170. Thus, the signal lines are impedance matched lines establishing a high frequency transmission bandwidth to the wafer 300 for supplying currents in a steady state as well as high current peaks generated by the device""s outputs switching in a transitional state. For removing noise, capacitors 193 and 195 are provided on the probe card between the power and ground planes.
An equivalent circuit of the probe card 170 is shown in FIG. 4 to explain the limitation of the high frequency performance in the conventional probe card technology. As shown in FIGS. 4A and 4B, the signal transmission line on the probe card 170 extends from the electrode 197, the strip (impedance matched) line 196, the wire 194 and the needle or cantilever (contact structure) 190. Since the wire 194 and needle 190 are not impedance matched, these portions function as an inductor L in the high frequency band as shown in FIG. 4C. Because of the overall length of the wire 194 and needle 190 is around 20-30 mm, significant limitations will be resulted from the inductor when testing a high frequency performance of a device under test.
Other factors which limit the frequency bandwidth in the probe card 170 reside in the power and ground needles shown in FIGS. 4D and 4E. If the power line can provide large enough currents to the device under test, it will not seriously limit the operational bandwidth in testing the device. However, because the series connected wire 194 and needle 190 for supplying the power (FIG. 4D) as well as the series connected wire 194 and needle 190 for grounding the power and signals (FIG. 4E) are equivalent to inductors, the high speed current flow is seriously restricted.
Moreover, the capacitors 193 and 195 are provided between the power line and the ground line to secure a proper performance of the device under test by filtering out the noise or surge pulses on the power lines. The capacitors 193 have a relatively large value such as 10 xcexcF and can be disconnected from the power lines by switches if necessary. The capacitors 195 have a relatively small capacitance value such as 0.01 xcexcF and fixedly connected close to the DUT. These capacitors serve the function as high frequency decoupling on the power lines. In other words, the capacitors limit the high frequency performance of the probe contactor.
Accordingly, the most widely used probe contactors as noted above are limited to the frequency bandwidth of approximately 200 MHz which is insufficient to test recent semiconductor devices. In the industry, it is considered that the frequency bandwidth comparable to the tester""s capability, which is currently on the order of 1 GHz or higher, will be necessary in the near future. Further, it is desired in the industry that a probe card is capable of handling a large number of semiconductor devices, especially memories, such as 32 or more, in a parallel fashion to increase test throughput.
In the conventional technology, the probe card and probe contactors such as shown in FIG. 3 are manually made, resulting in inconsistent quality. Such inconsistent quality includes fluctuations of size, frequency bandwidth, contact forces and resistance, etc. In the conventional probe contactors, another factor making the contact performance unreliable is a temperature change under which the probe contactors and the semiconductor wafer under test have different temperature expansion ratios. Thus, under the varying temperature, the contact positions therebetween vary which adversely affects the contact force, contact resistance and bandwidth.
Therefore, it is an object of the present invention to provide a contact structure for electrically contacting with a contact target which is capable of achieving a high frequency bandwidth, high pin counts and high contact performance as well as high reliability.
It is another object of the present invention to provide a contact structure such as a probe contactor to establish electrical connection in applications such as testing semiconductor devices and the like, having a very high frequency bandwidth to meet the test requirements in the next generation semiconductor technology.
It is a further object of the present invention to provide a contact structure to establish electrical connection in applications such as testing semiconductor devices, which are suitable for testing a large number of semiconductor devices in parallel at the same time.
It is a further object of the present invention to a contact structure to establish electrical connection in testing semiconductor devices, which are produced through a semiconductor production process without involving manual assembly or handling, thereby achieving consistent quality.
It is a further object of the present invention to provide a contact structure for establishing electrical connection in testing semiconductor devices which are produced through a micromachining process.
It is a further object of the present invention to provide contact structures to be mounted on a probe card for testing semiconductor devices which are capable of compensating temperature expansion coefficient of a semiconductor wafer under test.
In the present invention, a contact structure for establishing an electrical connection with a contact target is formed by a substrate of a planar surface on which a contactor is created by a microfabrication process established in the semiconductor technology.
The contact structure of the present invention is comprised of a substrate such as a silicon substrate and a contactor formed on the substrate through a micromachining process in which the contactor has a horizontal portion and a contact portion vertically formed on one end of the horizontal portion, wherein the horizontal portion of the contactor produces a contact force when the contactor is pressed against said contact target.
The contact structure further includes an interconnect trace on the substrate, one end of which is connected to the contactor while the other end is used for electrically connecting said contactor to an outer component. The contactor is made of metal and formed through a deposition process performed on a deposition area which has been directly formed by an electro-thermal energy generated by a micromachining tool. The contactor further comprises a base portion between the substrate and the horizontal portion where the base portion supports the horizontal portion and contact portion of the contactor.
Another aspect of the present invention is a contact structure having a recess. The contact structure includes a dielectric substrate having a recess (groove) on a surface thereof and a contactor formed on the substrate through a microfabrication process. The contactor is comprised of a horizontal portion having a fixed end and a free end, and a contact portion mounted on the free end of the horizontal portion. The fixed end is connected to the substrate and the free end is positioned over the recess on the substrate. The horizontal portion of the contactor produces a contact force when the contactor is pressed against the contact target such that the free end of the horizonal portion goes in the recess to exert a contact force.
According to the present invention, the contact structure has a very high frequency bandwidth to meet the test requirements of next generation semiconductor technology. Since the contact structure is formed through a modern miniaturization technology used in the semiconductor production process, a large number of contactors can be aligned in a small space which is suitable for testing a large number of semiconductor devices at the same time. The contact structure of the present invention can also be used in more general applications including an IC lead, IC packaging, and other electrical connections.
Since the large number of contactors are produced at the same time on the substrate with the use of the microfabrication technology without involving manual handling, it is possible to achieve consistent quality, high reliability and long life in the contact performance. Further, because the contactors can be fabricated on the same substrate material as that of the device under test, it is possible to compensate the temperature expansion coefficient of the device under test, which is able to avoid positional errors.